A FIFO is a memory unit that temporarily stores information so that when the data is retrieved the data first stored in the FIFO is the first data retrieved from the FIFO. The successive retrievals, therefore, output the stored data in the order in which they were inputted.
In many kinds of integrated circuits, particularly in those related to communications, there is a constant need to use FIFOs. In most cases, a FIFO is utilized to perform a buffering function. For example, in an integrated circuit, a FIFO can be used to buffer data that is being transmitted between two different circuit units controlled by two asynchronous clocking signals.
Similarly, if an integrated circuit is interfaced with an external microcomputer, data can be stored in a FIFO until there is a sufficient accumulation of data to start a continuous transmission of data between the integrated circuit and the microcomputer. Advantageously, this reduces the need for the microcomputer to execute an interrupt process in receiving data from the integrated circuit.
A conventional FIFO contains a data storage unit for storing a certain amount of data. Data is written into or is read out of the FIFO under the control of clock signals. When the FIFO is full and no more data can be written into it, a FULL Signal is generated. Similarly, when all of the data stored in the FIFO is read out, an EMPTY signal is generated.
To that end, the internal design of a conventional FIFO ordinarily comprises a plurality of regularly arranged memory units and a control unit which controls the writing of data into and the reading of data out of the memory units in response to the heretofore mentioned clock signals. The control unit also generates the FULL and EMPTY signals when the memory units are all FULL or all EMPTY.
When a FIFO is incorporated into an integrated circuit, the design of a central control unit is often a major undertaking. In particular, a separate design of the central control unit must usually be made for each FIFO of different size (i.e. different data storage capacity). In addition, because the centralized control unit is not modular, extra layout effort is required for an integrated circuit implementation.
One possible approach to this problem is modularization (see, e.g., Ward et al, U.S. Pat. No. 4,839,866 and Huang et al, U.S. Pat. No. 4,592,019). In particular, it would be highly advantageous if a FIFO comprising an expandable memory matrix section and control section could be devised so that a FIFO of arbitrary size could be produced simply by connecting the appropriate number of circuits. It is an object of the present invention to provide such a FIFO design. It is a further object of the invention to provide a simple and efficient control section that is especially easy to implement in an integrated circuit.